Microcontroller Systems

Dogan Ibrahim , in SD Card Projects Using the PIC Microcontroller, 2010

1.iii.11 EEPROM Data Retentivity

EEPROM type data retention is also very mutual in many microcontrollers. The advantage of an EEPROM is that the developer can store nonvolatile data in such a memory and can besides modify this data whenever required. For example, in a temperature monitoring awarding, the maximum and the minimum temperature readings tin be stored in an EEPROM. Then, if the power supply is removed for any reason, the values of the latest readings will still exist available in the EEPROM. The PIC18F452 microcontroller has 256 bytes of EEPROM. Some other members of the family unit have more (e.grand., PIC18F6680 has 1024 bytes) EEPROMs.

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Microcomputer systems

Dogan Ibrahim , in Arm-Based Microcontroller Multitasking Projects, 2021

1.2.4 EPROM

EPROM is erasable programmable read only retentivity. This is similar to ROM, only the EPROM tin can exist programmed using a suitable programming device. EPROM memories take a small clear glass window on height of the bit where the information can be erased under stiff ultraviolet light. Once the memory is programmed, the window tin be covered with dark tape to prevent accidental erasure of the information. An EPROM memory must exist erased before information technology can be reprogrammed. In the past, many development versions of microcontrollers were manufactured with EPROM memories where the user programs could exist stored. These memories have recently been replaced with wink memories. EPROM memories are erased and reprogrammed until the user is satisfied with the plan. Some versions of EPROMs, known as OTP (in one case programmable), tin can exist programmed using a suitable programmer device just these memories cannot be erased. OTP memories cost much less than the EPROMs. OTP is useful after a project has been developed completely and information technology is required to make many copies of the retentiveness chips.

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Retention ICs

Clive Max Maxfield , in Bebop to the Boolean Boogie (Third Edition), 2009

PROMs

The problem with mask-programmed devices is that creating them is a very expensive pastime unless you intend to produce them in extremely large quantities. Furthermore, such components are of piddling use in a evolution environment in which you often need to modify their contents.

For this reason, the first Programmable Read-Only Retentiveness (PROM) 17 devices were developed at Harris Semiconductor in 1970. These devices were created using a nichrome-based fusible-link eighteen applied science. As a generic example, consider a somewhat simplified representation of a transistor-and-fusible-link-based PROM cell (Effigy 15.10).

Effigy 15.10. A transistor-and-fusible-link-based PROM cell.

In its unprogrammed state every bit provided by the manufacturer, all of the fusible links in the device are nowadays. In this case, placing a row line in its agile state will plough on all of the transistors continued to that row, thereby causing all of the column lines to be pulled-down to logic 0 via their respective transistors. However, design engineers can selectively remove (blow) undesired fuses by applying pulses of relatively high voltage and current to the device's inputs. Wherever a fuse is removed ("blown"), that cell will appear to contain a logic 1.

PROMs were initially intended to be used every bit memories to store computer programs and constant data values (hence, the ROM portion of their appellation). Yet, design engineers also found them useful for implementing simple logical functions such equally lookup tables and state machines. The fact that PROMs were relatively cheap meant that these functions could be quickly modified to fix bugs or test new implementations by but called-for a new device and plugging it into the system.

PROMs are said to be Quondam Programmable (OTP), considering in one case you've programmed one and blown its fuses there's no going back. PROMs are slightly slower than their ROM equivalents, but are significantly cheaper for minor- to medium-sized production runs.

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Memory Devices, Nonvolatile

G. Baccarani , Due east. Gnani , in Encyclopedia of Condensed Matter Physics, 2005

Multi-Bit Memory Storage

The capacity of a flash EEPROM can be increased by storing two bits per jail cell, if four different threshold voltages, rather than 2, can be accommodated inside the prison cell. For a reliable performance, it is requested that the standard divergence associated with the statistical distribution of the threshold voltages be much smaller than the boilerplate separation between their central values. This may be accomplished with a tighter control of the injected accuse within the floating gate, and with a more sophisticated reading process. More than specifically, the threshold voltage must be monitored while programming, and the number and elapsing of writing pulses controlled by a suitable logic.

The reading process requires a number of steps involving two successive comparisons of the output electric current with iii reference currents made available past suitably programmed dummy cells. In doing then, the memory capacity is doubled for a given array size, at the expense of a degraded access time.

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Nanoelectromechanical Systems: Experiments and Modeling

H.D. Espinosa , ... Northward. Pugno , in Encyclopedia of Materials: Science and Technology, 2006

(b) Nanoelectromechanical programmable read-only memories

A germanium-nanowire-based nanoelectromechanical programmable read-only memory (NEMPROM) was reported by Ziegler et al. (2004). The device has two well-defined states considering of the coaction of the electrostatic energy, van der Waals energy, and elastic energy. The electrostatic forces pull in the nanowire to make contact with the electrode ("ON" state) and proceed the country even without the electrostatic field because the van der Waals force is larger than the electrostatic strength. The NEMPROM device tin can be switched OFF by mechanical move or past heating the device above the stability limit to overcome the van der Waals bonny forces. The working principle of the NEMPROM is like to that of the NRAM (Rueckes et al. 2000) since both of them apply van der Waals energy to reach the bistability behavior, although the usage of germanium may provide improve size command and electrical behavior than that of carbon nanotube.

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Programming Techniques

Martin Bates , in PIC Microcontrollers (Third Edition), 2011

6.4.4 EEPROM Memory

Motion picture fries have a block of electrically erasable programmable read-only memory (EEPROM), which operates as not-volatile, read and write memory, where the data is retained when the power is off. This is useful, for example, in applications such every bit electronic lock, where the correct combination tin can be stored for comparison with an input code, simply occasionally changed. Read from and write to EEPROM is illustrated in MPLAB in Effigy 6.8. The code sequence tin can exist seen in the source code window. Discover that the simulated input (09h) at port A is generated in a stimulus workbook window. The source code is listed every bit Program 6.4.

Figure vi.8. EEPROM operation: (a) register read process; (b) simulation of examination program EEP1

Program 6.4. EEPROM operation

The set of registers used to admission the EEPROM is EEDATA, EEADR, EECON1 and EECON2. The data to be stored is placed in EEDATA, and the address at which information technology is to be written in EEADR. Depository financial institution one must then be selected, and a read or write sequence included in the program as specified in the data canvas EEPROM section. The write sequence is designed to reduce the possibility of accidentally overwriting EEPROM, whereby essential data is lost. Reading the EEPROM is more than straightforward, every bit seen in the second sequence in the source code.

Other devices utilize a different technique to admission the EEPROM. For example, the eight-pivot PIC 12CE518/9 devices use series access via the unused bits of the port register. More recently introduced fries have extended the EEPROM write mechanism to include program memory read and write. The individual device data sheet must exist studied carefully before using this feature.

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Configuration

R.C. Cofer , Benjamin F. Harding , in Rapid System Prototyping with FPGAs, 2006

10.two On-Board Device Configuration

Different FPGA configuration approaches may exist supported. The most common modes are JTAG configuration, PROM configuration and processor configuration. As an example, both PROM and processor configurations modes tin can be implemented as either a serial or parallel configuration interface. Both of these modes may also exist implemented in either main or slave mode. The manner of operation will depend on the operational speed required, and the number and human relationship of the devices to be configured.

An FPGA synchronous serial interface typically requires five signals. A generalized clarification of the procedure follows. (Note that the signal names may be different for dissimilar FPGA manufacturers.) The required signals are information, clock, program command, set up, and complete. The data line sends the configuration data one bit at a time. The synchronous clock shifts the data into the FPGA. Data transfer typically occurs on the ascent border of the clock. The program command signal can place the FPGA in configuration mode or reset the FPGA. The ready line is asserted by the FPGA device when information technology is ready to start configuration. The consummate pin is asserted active past the FPGA when the configuration procedure is complete and the FPGA enters operational mode.

The other popular interface format is the parallel interface. This interface is asynchronous. Signals required to implement this interface include a parallel information bus, address signals, chip select, read and write and other control signals. A parallel interface can configure an FPGA at a faster rate, but the increased speed comes at the cost of using more than device pins.

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Introduction to the Moving picture microcontroller

D.Westward. Smith , in PIC in Practise (Second Edition), 2008

Program memory

Inside the microcontroller the plan we write is stored in an expanse chosen EPROM (Electrically Programmable Read Simply Retentiveness), this retention is non-volatile and is remembered when the ability is switched off. The retention is electrically programmed by a piece of hardware called a programmer.

The instructions we program into our microcontroller piece of work by moving and manipulating data in memory locations known as user files and registers. This memory is called RAM, Random Access Retentiveness. For instance in the room heater we would measure the room temperature by instructing the microcontroller via its Analogue to Digital Control Register (ADCON0) the measurement would then be compared with our data stored in 1 of the user files. A Status Register would indicate if the temperature was above or below the required value and a PORT Annals would turn the heater on or off accordingly. The memory map of the 16F84 chip is shown in Chapter vi.

Moving picture Microcontrollers are viii scrap micros, which ways that the memory locations, the user files and registers are made up of 8 binary digits shown in Figure 1.1.

Figure one.ane. User file and register layout

Bit 0 is the Least Significant Bit (LSB) and Bit 7 is the Almost Significant Bit (MSB).

The use of these binary digits is explained in Appendix C.

When you make an counterpart measurement, the digital number, which results, will exist stored in a register chosen ADRES. If you are counting the number of times a calorie-free has been turned on and off, the result would exist stored as an 8 bit binary number in a user file called, say, COUNT.

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Memory

Peter Wilson , in Pattern Recipes for FPGAs (2nd Edition), 2016

11.half dozen Flash Retention

As has been discussed previously, flash retentiveness is substantially a form of EEPROM (Electrically Erasable and Programmable Read Only Retentivity). This is slightly dissimilar from a standard RAM where the address is given to the retentiveness and depending on the R/West signals, the information is read or written, respectively. A typical set of interface pins for a flash retentiveness consists of the following elements:

Pin Role Active Country
CLE Control Latch H, activated on rising_edge(WE)
ALE Address Latch H, activated on rising_edge(We)
CE Chip Enable L
RE Read Enable Falling_edge(RE)
WE Write Enable Rising_edge(Nosotros)
WP Write protect L
decorated Set up/Decorated L = busy, H = ready

In addition to these control signals there is of form an accost bus and a data passenger vehicle. To implement this we tin utilise a similar entity to that for a standard RAM cake in VHDL:

1   entity flash is

2    generic (

3     a : natural := x;

4     d : natural := eight

v    );

6    port (

7     clk : in std_logic;

8     addr : in std_logic_vector(a−1 downto 0);

nine     information : inout std_logic_vector (d−1 downto 0);

10     cle : in std_logic;

eleven     ale : in std_logic;

12     ce : in std_logic;

thirteen     re : in std_logic;

fourteen     we : in std_logic;

xv     wp : in std_logic;

sixteen     busy : out std_logic;

17   );

18   cease entity flash;

In most cases we won't demand to model the wink memory itself, simply rather we demand to interface to information technology, then the entity for a flash interface controller could exist as follows:

1   entity flashif is

ii    port (

3     clk : in std_logic;

4     read : in std_logic;

5     en : in std_logic;

half dozen     cle : out std_logic;

seven     ale : out std_logic;

viii     ce : out std_logic;

9     re : out std_logic;

10     we : out std_logic;

eleven     wp : out std_logic;

12     busy : in std_logic;

13   );

14   end entity flashif;

A typical architecture for this device could be as follows:

one   architecture basic of flashif is

2   begin

three    process (clk) is

four     if busy =   ane   then

5     if rising_edge(clk) and so

6     ce <= en;

7     ale <=   1   ;

viii     cle <=   1   ;

9     if read =   0   so

x     we <=   1   ;

eleven     re <=   ane   ;

12     else

13     we <=   0   ;

fourteen     re <=   0   ;

15     end if;

sixteen     if prog =   0   then

17     wp <=   0   ;

eighteen     else

19     wp <=   ane   ;

xx     end if;

21     end if;

22     finish if;

23    end process;

24   finish architecture basic;

This is a basic outline for a flash controller and this volition obviously change from device to device.

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